Faithful Glitch Propagation in Binary Circuit Models
نویسندگان
چکیده
Modern digital circuit design relies on fast digital timing simulation tools and, hence, on accurate binary-valued circuit models that faithfully model signal propagation, even throughout a complex design. Of particular importance is the ability to trace glitches and other short pulses, as their presence/absence may even affect a circuit’s correctness. Unfortunately, it was recently proved [Függer et al., ASYNC’13] that no existing binary-valued circuit model proposed so far, including the two most commonly used pure and inertial delay channels, faithfully captures glitch propagation: For the simple Short-Pulse Filtration (SPF) problem, which is related to a circuit’s ability to suppress a single glitch, we showed that the quite broad class of bounded single-history channels either contradict the unsolvability of SPF in bounded time or the solvability of SPF in unbounded time in physical circuits. In this paper, we propose a class of binary circuit models that do not suffer from this deficiency: Like bounded single-history channels, our involution channels involve delays that may depend on the time of the previous output transition. Their characteristic property are delay functions which are based on involutions, i.e., functions that form their own inverse. A concrete example of such a delay function, which is derived from a generalized first-order analog circuit model, reveals that this is not an unrealistic assumption. We prove that, in sharp contrast to what is possible with bounded singlehistory channels, SPF cannot be solved in bounded time due to the nonexistence of a lower bound on the delay of involution channels, whereas it is easy to provide an unbounded SPF implementation. It hence follows that binary-valued circuit models based on involution channels allow to solve SPF precisely when this is possible in physical circuits. To the best of our knowledge, our model is hence the very first candidate for a model that indeed guarantees faithful glitch propagation.
منابع مشابه
A Faithful Binary Circuit Model with Adversarial Noise
Accurate delay models are important for static and dynamic timing analysis of digital circuits, and mandatory for formal verification. However, Függer et al. [IEEE TC 2016] proved that pure and inertial delays, which are employed for dynamic timing analysis in state-of-the-art tools like ModelSim, NC-Sim and VCS, do not yield faithful digital circuit models. Involution delays, which are based o...
متن کاملGlitch Power Reduction for Low Power IC Design
Because of the rapid growth of portable electronics, high density integrated circuits with low energy consumption and low electromagnetic interference (EMI) at high speeds are needed. It is well known that dynamic power dissipation is directly related to the number of the signal transitions in the circuit. Functional signal transitions are desirable, where spurious transitions (or glitches), ca...
متن کاملSymbolic Analysis of Circuit Reliability
Due to shrinking feature size and significant reduction in noise margins, nanoscale circuits have become more susceptible to manufacturing defects, noise-related transient faults and interference from radiation. Traditionally, soft errors have been a much greater concern in memories than in logic circuits. However, as technology continues to scale, logic circuits are becoming more susceptible t...
متن کاملModeling of Single Spin Logic Based Hazard Free Network
Modern CMOS based advanced digital circuits suffer unwanted switching transients referred as ‘hazard’, due to ununilateral propagation delays. The hazard in combinational circuit results from a single variable change when the output should not have been altered or manipulated. The hazardous behavior of the logic circuit often creates a glitch. The glitching effect is negligible in very small ci...
متن کاملLow power transformation of datapath architectures with cyclic SFGs
Datapath architectures exhibit a large amount of undesired switching (glitches) which does not contribute to the functionality but leads to increased power consumption. While glitch propagation can be effectively reduced by pipelining circuits with acyclic SFGs, this technique is not directly applicable if the circuit contains loops. The paper addresses this problem and discusses a methodology ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- CoRR
دوره abs/1406.2544 شماره
صفحات -
تاریخ انتشار 2014